Alex Forencich
Emerging

Alex Forencich

@alexforencich

UC San Diego

www.alexforencich.com
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Eternal Developer
La Jolla, CA
coderank.me

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Verilog55%
Python45%
Verilog55%
PythonPython45%

Top Repositories

10 shown of 73 repos · 9,713 stars
verilog-ethernetVerilog

Verilog Ethernet components for FPGA implementation

3,078853
verilog-axiVerilog

Verilog AXI components for FPGA implementation

2,123541
verilog-pcieVerilog

Verilog PCI express components

1,650421
verilog-axisPython

Verilog AXI stream components for FPGA implementation

810248
verilog-i2cVerilog

Verilog I2C interface for FPGA implementation

727196
verilog-uartVerilog

Verilog UART

493140
cocotbext-axiPython

AXI interface modules for Cocotb

356117
cocotbext-pciePython

PCI express simulation framework for Cocotb

19859
verilog-dspPython

Verilog digital signal processing components

14338
verilog-wishbonePython

Verilog wishbone components

13537